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[Otherrs-codec-8-16

Description: 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
Platform: | Size: 132096 | Author: yuanfeng | Hits:

[ELanguagers-codec-8-4

Description: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien - search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data - rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Platform: | Size: 44917 | Author: zs8292 | Hits:

[Other resourceRS(204_188)decoder

Description: <Verilog HDL 语言编程》 RS(204,188)译码器的设计
Platform: | Size: 11406 | Author: 李映波 | Hits:

[Otherrs-codec-8-16

Description: 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
Platform: | Size: 133120 | Author: yuanfeng | Hits:

[Othermanydecoders_V

Description: 各种解码译码电路模型的VerilogHDL描述-various decoder decoding circuit model of Verilog HDL description
Platform: | Size: 2048 | Author: nil | Hits:

[ELanguagers-codec-8-4

Description: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data- rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Platform: | Size: 45056 | Author: zs8292 | Hits:

[VHDL-FPGA-Verilogrs_decoder_31_19_6.tar

Description: Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register. -Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15* 21 ^ 6 a X* X ^ a ^ 15 2* X ^ a ^ 3 25* X ^ a ^ 4 17 5* X ^ a ^ 18 ^ 6 X* a* X 30 ^ 7 ^ a ^ 20* X ^ a ^ 23 8* X ^ a ^ 9* 27 X 10 ^ a ^ 24* 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Platform: | Size: 14336 | Author: 许茹芸 | Hits:

[VHDL-FPGA-VerilogRS(32to28)encoderanddecoder

Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: | Size: 76800 | Author: 王文 | Hits:

[VHDL-FPGA-VerilogRS(204_188)decoder

Description: <Verilog HDL 语言编程》 RS(204,188)译码器的设计-<Verilog HDL language programming RS (204,188) Decoder
Platform: | Size: 11264 | Author: 李映波 | Hits:

[VHDL-FPGA-VerilogRSdecoder

Description: cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program
Platform: | Size: 13312 | Author: 陈臣 | Hits:

[VHDL-FPGA-Verilogc23_RS_decoder

Description: 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
Platform: | Size: 13312 | Author: 李平 | Hits:

[VHDL-FPGA-Verilogrs-codec-8-16

Description: RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: | Size: 27648 | Author: 饶进平 | Hits:

[OtherRS(204.188)design

Description: RS(204,188)译码器说明 原文件: rs_decoder.v(顶层文件), SyndromeCalc.v(计算伴随式), BM_KES.v(BM求解关键方程), Forney.v(Forney算法求误差样值), CheinSearch.v(搜索错误位置),ff_mul.v(有限域乘法)。 ROM及初始化文件: rom_inv.v(求逆运算), rom_power.v(求幂运算); rom_inv.mif(ROM初始化文件), rom_power.mif(ROM初始化文件)。 仿真波形: rs_decoder.vwf。-RS (204,188) decoder that the original document: rs_decoder.v (top-level document), SyndromeCalc.v (calculated Syndrome), BM_KES.v (BM key equation solving), Forney.v (Forney algorithm for error-like value), CheinSearch.v (search the wrong location), ff_mul.v (finite field multiplication). ROM and the initialization file: rom_inv.v (inverse operation), rom_power.v (for power calculations) rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization files). Simulation waveforms: rs_decoder.vwf.
Platform: | Size: 14336 | Author: 川天古木 | Hits:

[VHDL-FPGA-Verilogrs_decoder204_188

Description: RS译码的Verilog实现,用的是改进的BM算法,已在QuautusII9.0上调试通过-rs decoder verilog
Platform: | Size: 9468928 | Author: songbing | Hits:

[VHDL-FPGA-VerilogRS

Description: RS译码器的设计源程序--verilog HDL实现-Design of the RS decoder source code-- Verilog HDL
Platform: | Size: 14336 | Author: 王垚 | Hits:

[OtherRS_dec

Description: rs(204,188)译码器,verilog实现,乘法器采用比特异或方式实现-rs (204,188) decoder, verilog achieve multiplier used than specific or way
Platform: | Size: 13312 | Author: 洋洋 | Hits:

[VHDL-FPGA-VerilogRS

Description: 通过verilog hdl语言实现RS编码器与译码器的设计-Verilog hdl language through the RS encoder and decoder design
Platform: | Size: 26624 | Author: 李永超 | Hits:

[Otherrs_decoder_31_19_6.tar

Description: RS Decoder RTL verilog Code
Platform: | Size: 14336 | Author: richman | Hits:

[Communication-Mobilers_15_11

Description: ReedSolomon RS(15,11) Verilog 编码和解码测试程序 编码有两种实现方式 串行和并行方式(ReedSolomon RS(15,11) Verilog Encoder&Decoder)
Platform: | Size: 14336 | Author: Ericxgj | Hits:

[VHDL-FPGA-VerilogRS(204,188)译码器的设计

Description: RS(204,188)译码器说明 原文件: rs_decoder.v(顶层文件), SyndromeCalc.v(计算伴随式), BM_KES.v(BM求解关键方程), Forney.v(Forney算法求误差样值), CheinSearch.v(搜索错误位置),ff_mul.v(有限域乘法)。 ROM及初始化文件: rom_inv.v(求逆运算), rom_power.v(求幂运算); rom_inv.mif(ROM初始化文件), rom_power.mif(ROM初始化文件)。 仿真波形: rs_decoder.vwf。(RS (204188) decoder explanation Original document: Rs_decoder.v (top level file), SyndromeCalc.v (Computational adjoint), BM_KES.v (BM solving key equations). Forney.v (Forney algorithm for error sample), CheinSearch.v (search wrong location), ff_mul.v (finite field multiplication). ROM and initialization files: Rom_inv.v (inverse operation), rom_power.v (exponentiation operation). Rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization file). Simulation waveform: Rs_decoder.vwf.)
Platform: | Size: 15360 | Author: HelloFrank0 | Hits:
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